With the rapid development of semiconductor manufacturing technology, semiconductor devices are developing towards a direction of higher component density and a higher degree of integration. Transistors as the most basic semiconductor devices are currently being widely used and, with the increasing of the semiconductor device component density and the integration degree, the transistor size is getting smaller and smaller.
In a fin field effect transistor (Fin FET), the channel is projected over the surface of the substrate to form a fin structure, and the gate covers the top and sidewalls of the fin structure. As such, the inversion layer formed on each side of the channel can control the turning-on and turning-off of the circuit on both sides, thereby greatly improving the circuit control and reducing the leakage current. In addition, the 3D architecture of a Fin FET can improve the integration of the Fin FET. However, the width of the fin structure of a Fin FET may be relatively narrow, which can make the cooling of the Fin FET to be a significant challenge. Therefore, a self-heat problem of the Fin FET may be caused, which can damage the fin structure of the Fin FET.
Especially, in an electrostatic discharge circuit, a large electrostatic current generated by external circuitry can flow into the drain of the electrostatic discharge circuit, which may easily lead to a sharp increase of the temperature of the drain, causing an instable performance of the electrostatic discharge device. Therefore, the heat dissipation performance of the electrostatic discharge circuit has a significant impact on the electrostatic discharge device.
Accordingly, the existing fin field-effect transistors have the disadvantages of poor heat dissipation and instable transistor performance. The disclosed electrostatic discharge protection structure and fabricating method thereof are directed to solve one or more problems set forth above and other problems.